Encryption-based data transmission schemes generally encode data using a random key. The original data may be referred to as plain text, the encryption key referred to as the keystream, and the resulting encrypted data referred to as the cipher text. The terms bits will sometimes be used in place of text in this description to indicate the binary representation of the text.
A transmitter encodes data using a selected keystream, and a receiver decodes the data using the same keystream. In some applications the receiver may be initially unaware of the keystream used by the transmitter. In these applications, the receiver applies different keystreams to received cipher text until the cipher text is successfully decoded. The keystream may be determined from a training pattern that is sent by the transmitter and known to the receiver. Once the receiver has decoded the cipher text using a keystream and recognized the training pattern, the receiver is said to have locked onto the training pattern. Thereafter, that keystream provides the seed for subsequently generated keystreams.
Serial encryption circuitry is often implemented with a linear feedback shift register (LFSR) that generates a serially output keystream. The cipher text may be generated by applying an exclusive-or function to the bits of plain text in combination with bits of the keystream. The output bits of the keystream are also fed back as input to the first stage of the LFSR.
For an LFSR having n stages and that implements a complete sequence, the maximum time that a receiver may expend in locking onto the training pattern is 2n−1 cycles. For large keystreams this may be a performance issue.
With increasing speeds and increasing numbers of configurable resources, field programmable gate arrays (FPGAs) are becoming the device of choice to implement various application circuitry. However, an FPGA may be unsuitable to host a serial LFSR that is to operate at very high frequencies. Even though an FPGA may be unable to implement an LFSR operating at some highest clock-rate, the speed limitations of the FPGA may be ameliorated by multiplexing the LFSR output into a parallel representation.
One method of multiplexing the serial LFSR sequence into a parallel sequence is to clock the serial LFSR at a high rate, and then perform a serial to parallel conversion to the slower rate parallel version. This process is reversed to demultiplex the low-speed parallel version into the higher-rate serial sequence. This process may be expensive in terms of resources because it requires logic for both the serial LFSR and the serial to parallel conversion.
The serial to parallel conversion of an LFSR sequence may result in a number of possible variations of the encoded training pattern since the keystream may vary according to the time at which the serial keystream is parallelized. The possible variations in the parallel form of the training pattern may require many cycles for the decoder to lock on the training pattern because the decoder must attempt different keystreams with the variations in the training pattern.
The present invention may address one or more of the above issues.